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Pixel Data Processing Overview

Global description of the image pixel data processing chain

The Image Pixel Data Processor performs the following successive operations on the image data stream:

CoaXPress bit stream slicing

This operation extracts individual pixel components data from the CoaXPress image data bit stream according to the bit depth – input-bit-depth – specified by the 'PixelF' property of the CoaXPress Image Header.

All components have the same pixel bit depth. Possible values are 8-/10-/12-/14- and 16-bit.

The slicer delivers, for each image line, all the pixel components necessary to build a number of pixels specified by the 'Xsize' property of the CoaXPress Image Header.

The slicer discards CoaXPress line-padding data.

Lookup Table processing

This operation performs lookup table processing on individual pixel components.

For more information and configuration instructions, refer to Lookup Table Processing.

Pixel component unpacking

This operation unpacks 10-bit, 12-bit, and 14-bit pixel components to 8-bit or 16-bit.

It can be disabled for monochrome and Bayer CFA pixel formats.

For more information and configuration instructions, refer to Pixel Component Unpacking.

Pixel component ordering

This operation modifies the component order of multi-components pixel data.

For more information and configuration instructions, refer to Pixel Component Ordering.

Endianness conversion

This operation modifies the byte order of 16-bit pixel component data.

For more information, refer to Endianness Conversion.

Image line build-up

This operation builds concatenates the components data of all pixels of an image line:

  • 8-bit pixel components are aligned to byte boundaries
  • 16-bit pixel components (possibly expanded by unpacking or lookup table processing) are aligned to word (2-byte) boundaries, the 2 bytes are stored according to the little-endian convention.

Line padding

This operation appends padding bits or bytes to the image line data to reach the next alignment-boundary required by the hardware implementation.

The alignment boundary requirements are product-specific, for instance:

  • 64-bit for 1630 Coaxlink Mono, 1631 Coaxlink Duo, and 1632 Coaxlink Quad
  • 128-bit for 1633 Coaxlink Quad G3 and 1635 Coaxlink Quad G3 DF

Processing Performances

The pixel processor sustain the highest camera pixel rate. All the above operations are executed while transferring data to the GenTL with a negligible latency. However, particularly when the bit depth is increased, the amount of pixel data to transfer is increased accordingly. In that case, the PCI Express bandwidth limitation may negatively impact the achievable frame- or line-rate.