CIC Synchronization Timing Diagram
CIC Synchronization through C2C-Link timing diagram
The above diagram shows the timing diagram of two consecutive common Cycle Start events:
The C2C-Link Global Ready signal is held low until the Ready of all participating devices is true preventing the C2C-Link Master to issue a start event. When released by all participating devices, it ramps up rapidly with a rise time of maximum 100 ns.
As soon as the C2C-Link Global Ready signal is confirmed to be high, the master device asserts an abrupt going low transition on the Common Cycle Start signal; this edge is propagated to all the Start inputs of the timers of all participating devices.
As soon as the cycle has started, every CIC forces the ready low as long as all the local conditions to initiate the next cycle are not satisfied.
The timers of each device issue a Camera Trigger and a Strobe, with their respective delay and duration settings. Usually, the settings are identical for all participating devices; but the application is allowed to apply different ones, if needed.
The shortest Cycle Start period allowed by the C2C-Link is 400 ns; allowing a theoretical frequency limit of 2.5 MHz.