RateDivisionFactor
Division factor of the line trigger rate divider
Applicable product(s): 1624 Grablink Base, 1623 Grablink DualBase, 1622 Grablink Full, 1626 Grablink Full XR.
Parameter Info
Class | Category | Level | Type | Access |
---|---|---|---|---|
Channel | Encoder Control | ADJUST | Integer | Set and Get |
Num ID | String Identifier | C, C++ identifier |
---|---|---|
10553 << 14 | RateDivisionFactor | MC_RateDivisionFactor |
Parameter Description
The rate divider circuit generates a line trigger signal at a frequency that is an integer fraction 1/N of the frequency of the pulses delivered by the quadrature decoder circuit.
For N consecutive incoming pulses issued by the quadrature decoder circuit, the 1/N rate divider:
- Generates one output pulse (one line trigger)
- Skips N-1 input pulse
The rate divider is initialized at the beginning of every MultiCam acquisition sequence. The first output pulse is produced from the first clock input pulse occurring after the sequence trigger event.
Notice that:
- The output frequency is lower than (N > 1) or equal to (N = 1) the input frequency. It cannot be higher.
- The output pulse is generated with a small fixed delay after a non-skipped input pulse. The line trigger pulses are phase-locked to the quadrature decoder output.
- The rate divider settings may not be modified while acquisition is in progress.
Parameter Values
Numeric values: 1, 512
1 |
Always applicable. Default value. |
512 |
Always applicable. |